A clock signal may be distributed throughout a processor to facilitate the processor's operation. For example, state elements located at different points in the processor die may function synchronously by operating in accordance with the clock signal.
FIG. 1 illustrates a traditional circuit 100 that may be used to distribute a clock signal throughout a processor. A Phase-Locked Loop (PLL) unit 110 synthesizes a high frequency clock signal that is then distributed through a clock distribution “tree.” That is, the clock signal reaches a destination 130 by traveling through a path in the tree via a number of inverters 120.
To enable the state elements in the processor to function synchronously together, the tree is designed so that the different paths in the circuit 100 are matched (e.g., the clock signal will pass through the same number of inverters 120 and therefore arrive at each destination 130 at substantially the same time).
A number of problems may arise, however, when a clock signal is distributed via a traditional clock distribution tree. For example, a large processor die and/or a large number of devices may require a lengthy distribution tree. Such a lengthy distribution tree may result clock signal inaccuracies (e.g., a clock signal received at one device may be skewed as compared to a clock signal received at another device). Moreover, a high frequency clock signal may require the use of repeaters in the distribution tree, which can further contribute to clock signal inaccuracies. In addition, small device geometries (e.g., device dimensions) may cause printing inaccuracies that can increase clock signal inaccuracies. Note that any inaccuracies in the clock signal may need to be accounted for in the processor's timing budget (e.g., the inaccuracies may become a significant portion of the clock period and reduce the processor's performance).
Another problem may be associated with an inefficient use of power in a processor. In a traditional clocking system, a fixed frequency is synthesized by a PLL unit from an external reference clock supplied by the system. When the current drawn by the processor suddenly changes, the supply voltage in the core may collapse (i.e., “droop”) even though the frequency remains constant as generated by the PLL unit. Therefore, to guarantee functionality in this case, the circuit may be designed to operate at the highest specified frequency and at the lowest potential voltage—even though these droops events may be infrequent. The effect of the voltage droops can be reduced by adding sufficient decoupling capacitors and by using an elevated supply voltage. This approach, however, may waste power and increase the cost of the die.